Apple is reportedly building an AI server chip with Broadcom • The Register

Apple is reportedly working with chip giant Broadcom to develop a custom server processor to power the AI services and features built into its operating systems.

According to The Information, which cites three unnamed sources with knowledge of the matter, the project is codenamed “Baltra” and is expected to enter production in 2026.

Beyond this, details are predictably pretty thin. At the iGiant’s developer conference earlier this year, Craig Federighi, SVP of software engineering, declared that Apple Intelligence would run both on-device and in a private cloud using servers powered by Apple Silicon.

The idea that Apple might be building custom chips for GenAI isn’t surprising. The iBiz has designed its own Arm-based silicon for years. The idea that Broadcom might be involved in this process shouldn’t come as a shock either as the two companies already work together on 5G componentry.

Broadcom is a massive conglomerate that, among other things, licenses intellectual property for use in semiconductor designs – particularly in the field of high-speed networking. For instance, back at the Hot Chips conference we looked at an optical interconnect chiplet designed to be packaged alongside GPUs and other accelerators to support larger scale-up compute clusters.

More recently, Broadcom showed off its 3.5D packaging tech, which is designed to help chipmakers scale beyond reticle limits – similar to what Intel has done with its Ponte Vecchio (GPU Max) GPUs.

AMD used similar techniques AMD to build its MI300X accelerators, which combine eight compute chiplets and vertically stack them on top of four I/O dies which handle memory management and chip-to-chip communication.

Boadcom’s 3.5D XDSiP demo chip seen here looks surprisingly similar to AMD’s MI300X, but is open to anyone to license – Click to enlarge

Broadcom’s 3.5D eXtreme Dimension System in Package tech – 3.5D XDSiP for short – is essentially a blueprint that customers can use to build multi-die processors of their own. Like AMD’s MI300X it stacks compute dies on top of a logic die that interfaces with high bandwidth memory (HBM), but breaks out other I/O functionality into a separate set of dies.

Broadcom’s approach to interfacing compute dies interface with the rest of the system logic is a little different. According to Broadcom, previous 3.5D packaging technologies have used face-to-back approaches, which require more work to route through silicon vias (TSVs) which shuttle data between the two.

Broadcom’s design uses a face-to-face approach, which allows for denser electrical interfaces between the chiplets using hybrid copper bonding (HBC). We’re told this will allow for substantially higher die-to-die interconnect speeds and shorter signal routing.

The largest of these designs will support two 3D stacks, a pair of I/O chiplets, and up to 12 HBM3 modules on a single package totaling more than 6,000 mm^² of silicon area. Broadcom expects the first parts based on these designs to enter production in 2026.

Coincidentally, that’s the same timeline that The Information reports Apple’s project Baltra is aiming at.

It is unclear if the two projects are related. However some Apple chip designs – the M2 Ultra for instance – already make use of multi-die architectures, so it’s not a stretch to suggest some overlap.

We likely will not know much more about Baltra until it becomes reality. Apple is notoriously tight-lipped about products before they’re officially announced. And while Broadcom is always happy to discuss its chip tech, it’s highly secretive about who’s actually buying it. Apparently that list includes some pretty big names – for instance, Google reportedly made extensive use of Broadcom IP in its Tensor Processing Units (TPUs). It’s not a stretch to imagine Apple taking advantage of existing technologies rather than reinventing the wheel.

The Register sought comment from Broadcom and Apple. Unsurprisingly, neither had responded at the time of publication. ®